Achtergrond van Bruco

A 10Gb/s Serial Communication Transceiver in 0.13µm CMOS for a 2m Micro Twisted-Pair Cable

Pixel chips for future applications produce a virtually infinite amount of data. For imaging, there is a need for more frames per second, while high energy physics experiments will run at a higher luminosity, meaning more hits per second. All this data has to be transported off the pixel chip.

Large Hadron Collider beauty experiment

The Large Hadron Collider beauty (LHCb) experiment is one of the four large experiments based at CERN. The aim of the LHCb experiment is to record the decay of particles containing b and anti-b quarks, collectively known as ‘B mesons'. The experiment's 4,500 tonne detector is specifically designed to filter out these particles and the products of their decay. Pixel chip modules (VeloPix) are located very close to the point where the collisions take place.
For the upgrade of the LHCb experiment, the expected link speed needed for the pixel modules is about 10Gb/s. Because of the extreme radiation dose, optical transceivers are not directly placed onto the pixel modules, but on optical modules that are placed 1 to 2m away from the pixel modules. This separation greatly reduces the radiation level at the optical modules and simplifies the design and production of both the pixel modules and the optical modules.

Challenge

The electrical data transmission between pixel modules and optical modules is done over micro twisted-pair cables. To disturb the measurements as little as possible, the material budget must be minimized. Therefore the twisted-pair cables are very thin. The small cross-section of the cables limits the bandwidth severely. The transfer function for a characteristically terminated cable of 2m has already a loss of 42dB at 5GHz. This makes communication at a data rate of 10Gb/s challenging.

Solution

In order to achieve a data rate of 10Gb/s, equalization is needed. Pulse-width modulation turns out to be the best equalization method. However, the eye-height at the receiver is very sensitive towards the exact value of the pulse-width. A more robust system is created if the source impedance of the transmitter is equal to a parallel resistance and capacitance, whose values are matched to the cable. This also makes the transceiver robust against bondwire inductance.
Chip photograph of 10Gb/s tranceiver
A chip was designed in a 0.13 µm 1.2V process. Current-Mode Logic (CML) cells were used throughout the design to meet the speed requirements. Some critical blocks use inductive peaking. In the receiver, high gain is achieved by a cascade of CML buffers. A DC feedback loop is used to compensate for offset.

Further reading

This work was published at the TWEPP 2010 and the proceedings can be found here.