Development of a single chip 0.18µm CMOS Zigbee TransceiverFor short-range wireless networking, several communication standards have been developed like Bluetooth (IEEE 802.15.1), WiFi (IEEE 802.11 a, b, g, n) and ZigBee (IEEE 802.15.4). The ZigBee standard has, different from the other standards, its focus on low-power consumption to enable for example energy harvesting techniques to power the transceiver. Typical applications for ZigBee transceivers are remote controls and wall switches.
To obtain a low-cost solution with a small bill of materials, we developed a single-chip CMOS ZigBee tranceiver. This means that the analog receiver and transmitter blocks are integrated with the digital baseband processing blocks on one single piece of silicon. As the digital part of the transceiver represents a significant amount of chip area, the choice for CMOS is obvious.
The technology choice, driven by the digital circuitry, is CMOS but it is not necessary the best solution when viewed from an analog perspective. In the analog domain, where gain, bandwidth, noise and offsets are the dominant factors, bipolar transistors will easily outperform MOS devices on most of these parameters for a given current.
As the transceiver operates in an un-licensed frequency band, many users can be encountered. Therefore parameters like sensitivity, selectivity and immunity to large signals are important to the receiver, as well as signal purity and spectrum mask conformity are to the transmitter. For link optimization antenna diversity is required by means of an integrated antenna switch. Besides the challenging dynamic range requested from the analog blocks, also the immunity to substrate noise from the digital baseband processing part is key for reaching a good sensitivity of the receiver and a clean spectrum of the transmitter.
To obtain a very high level of integration, the zero- and low-IF architectures are in principle best suitable for both the receiver and the transmitter part. However, the used modulation (O-QPSK) happens to have serious content around DC and therefore any DC-offset, a typical issue in zero-IF receivers, is difficult to cope with. Therefore a low-IF architecture is chosen for the ZigBee receiver. For the transmitter, the offsets associated with zero-IF systems are less of a problem because unwanted carrier feed-thru can be easily calibrated out to acceptable levels. Therefore the transmitter has a zero-IF architecture.
An important part of the solution is given by the choice of the CMOS process. In our design we use a process that has a relatively high-Ohmic substrate, thick metal options and isolated p-wells in the p-substrate (triple-well isolation). This is very beneficial for having high quality integrated inductors, enabling the integration of the complete VCO and obtaining a good noise-figure in the LNA. The sensitive circuits are placed in isolated wells with local substrate connections and use differential signaling to obtain maximum substrate noise immunity.